The present invention relates to integrated circuits (ICs) and methods of manufacturing integrated circuits. More particularly, the present invention relates to a transistor and a method of manufacturing the transistor. The transistor is advantageously less susceptible to short channel effects.
Integrated circuits (ICs), such as, ultra-large scale integrated (ULSI) circuits, can include as many as one million transistors or more. The ULSI circuit can include complementary metal oxide semiconductor (CMOS) field effect transistors (FETS). The transistors can include conducive gates disposed between drain and source regions. The drain and source regions are typically heavily doped with a P-type dopant (boron) or an N-type dopant (phosphorous).
The drain and source regions generally include a thin or shallow extension that is disposed partially underneath the gate to enhance the transistor performance. Shallow source and drain extensions help to achieve immunity to short-channel effects, which degrade transistor performance for both N-channel and P-channel transistors. Short-channel effects are among the most important scaling issues for mainstream CMOS technology and can cause threshold voltage roll-off and drain-induced barrier lowering. Shallow source and drain extensions and, hence, controlling short-channel effects, are particularly important as transistors become smaller.
Conventional techniques utilize a double implant process to form shallow source and drain extensions. According to the conventional process, the source and drain extensions are formed by providing a transistor gate structure without sidewall spacers on a top surface of a silicon substrate. The silicon substrate is doped on both sides of the gate structure via a conventional doping process, such as, a diffusion process or an ion-implantation process. Without the sidewall spacers, the doping process introduces dopants into a thin region (i.e., just below the top surface of the substrate) to form the drain and source extensions as well as to partially form the drain and source regions.
After the drain and source extensions are formed, silicon dioxide spacers, which abut lateral sides of the gate structure, are provided over the source and drain extensions. The substrate is doped a second time to form the deeper source and drain regions. The source and drain extensions are not further doped due to the blocking capability of the silicon dioxide spacer.
As transistors disposed on integrated circuits (ICs) become smaller, transistors with shallow and ultra-shallow source/drain extensions have become more difficult to manufacture. For example, smaller transistors should have ultra-shallow source and drain extensions (less than 30 nanometer (nm) junction depth). Forming source and drain extensions with junction depths of less than 30 nm is very difficult using conventional fabrication techniques.
Conventional ion-implantation and diffusion-doping techniques make transistors on the IC susceptible to short-channel effects, which result in a dopant profile tail distribution that extends deep into the substrate. Also, conventional ion-implantation techniques have difficulty maintaining shallow source and drain extensions because point defects generated in the bulk semiconductor substrate during ion implantation can cause the dopant to more easily diffuse (transient enhanced diffusion, TED). The diffusion often extends the source and drain extensions vertically into the bulk semiconductor substrate.
Furthermore, as transistors disposed on integrated circuits (ICs) become smaller (e.g., transistors with gate lengths approaching 70 nm or less), source and drain extension depths need to be aggressively reduced to achieve acceptable immunity to the short-channel effect. For example, a transistor having a gate length of less than 70 nm should have an ultra-shallow source/drain extension (e.g., depth of 10-20 nm). However, the formation of the ultra-shallow source/drain extension is very difficult with conventional ion implantation and thermal annealing techniques. For example, ultra-shallow source/drain extensions are susceptible to significant dopant loss during the low-KeV implantation, as well as to increased transient-enhanced diffusion (TED), which make the junction depth much deeper. These problems can prevent the manufacture of a ULSI integrated circuit having transistors with gate lengths of less than 50 nm.
Another important factor associated with reduced transistor size relates to transistor leakage current. As the physical length of the gate is reduced to increase the transistor on-state drive current, the spacing between the source and drain extensions becomes closer. The off-state leakage current dramatically increases as the source/drain extensions become closer. Increased off-state leakage current increases the power consumption and heat generated by an integrated circuit.
Thus, there is a need for a transistor that has source and drain extensions that are not formed by conventional processes. Further still, there is a need for a transistor with less susceptibility to short-channel effects. Further still, there is a need for source/drain extensions that do not contribute significantly to off-state leakage current. Even further still, there is a need for a method of making a novel transistor structure that is less susceptible to short channel effects.
One exemplary embodiment relates to a transistor with electrically induced source/drain extensions. The transistor includes a source, a drain, and a gate structure. The gate structure is disposed between the source and the drain and has a first gate electrode and a second gate electrode. The second gate electrode provides the electrically induced source/drain extensions. The first gate electrode turns the transistor on when a signal or voltage is applied to the first gate electrode.
Another exemplary embodiment relates to a circuit comprising a transistor having a gate electrode means for receiving a gate signal. The transistor is in an on state in response to a gate signal having a first level and is in an off state in response to the gate signal having a second level. Source/drain extensions are formed in response to a gate bias.
Yet another exemplary embodiment relates to a method of fabricating an integrated circuit on a substrate. The integrated circuit includes at least one transistor with electrically induced source/drain extensions. The method includes providing a first gate conductor on a substrate, providing a dielectric layer over the first gate conductor, and providing a second gate conductor over the dielectric layer above the first gate conductor. The second gate conductor is capable of forming electrically induced source/drain extensions.
Still another exemplary embodiment relates to a transistor. The transistor includes a source region, a drain region, and a gate structure. The gate structure is disposed between the source region and the drain region. The transistor is in an on state in response to a gate signal having a first level and is in an off state in response to the gate signal having a second level. The gate structure includes a first gate electrode for forming the source and drain extensions and a second gate electrode for receiving the gate signal.